Representing Architecture Constraints in Ursa

Architectural features such as pipelines, instructions that use registers implicitly, and instructions that can be executed on any of several types of functional units require a tightly integrated instruction scheduler and register allocator. Such an integrated system can detect the interactions between the various problems that must be solved and therefore improve the use of available resources. In this paper we show that the resource requirements framework developed in URSA for unifying instruction scheduling and register allocation is powerful enough to represent the problems presented by these architectural features. Thus, all of the problems can be addressed in a uniform manner and in conjunction with instruction scheduling and register allocation. URSA's representation can also incorporate a new algorithm for assigning instructions to functional units to reduce interlock delays in pipelined multiple issue architectures.